| CMSIS-CORE Version 3.20 CMSIS-CORE support for Cortex-M processor-based devices

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Functions
Intrinsic Functions for CPU Instructions

## Functions
void | __NOP (void)
| No Operation. More...
void | __WFI (void)
| Wait For Interrupt. More...
void | __WFE (void)
| Wait For Event. More...
void | __SEV (void)
| Send Event. More...
void | __BKPT (uint8_t value)
| Set Breakpoint. More...
void | __ISB (void)
| Instruction Synchronization Barrier. More...
void | __DSB (void)
| Data Synchronization Barrier. More...
void | __DMB (void)
| Data Memory Barrier. More...
uint32_t | __REV (uint32_t value)
| Reverse byte order (32 bit) More...
uint32_t | __REV16 (uint32_t value)
| Reverse byte order (16 bit) More...
int32_t | __REVSH (int32_t value)
| Reverse byte order in signed short value. More...
uint32_t | __RBIT (uint32_t value)
| Reverse bit order of value [not for Cortex-M0 variants]. More...
uint32_t | __ROR (uint32_t value, uint32_t shift)
| Rotate a value right by a number of bits. More...
uint8_t | __LDREXB (volatile uint8_t *addr)
| LDR Exclusive (8 bit) [not for Cortex-M0 variants]. More...
uint16_t | __LDREXH (volatile uint16_t *addr)
| LDR Exclusive (16 bit) [not for Cortex-M0 variants]. More...
uint32_t | __LDREXW (volatile uint32_t *addr)
| LDR Exclusive (32 bit) [not for Cortex-M0 variants]. More...
uint32_t | __STREXB (uint8_t value, volatile uint8_t *addr)
| STR Exclusive (8 bit) [not for Cortex-M0 variants]. More...
uint32_t | __STREXH (uint16_t value, volatile uint16_t *addr)
| STR Exclusive (16 bit) [not for Cortex-M0 variants]. More...
uint32_t | __STREXW (uint32_t value, volatile uint32_t *addr)
| STR Exclusive (32 bit) [not for Cortex-M0 variants]. More...
void | __CLREX (void)
| Remove the exclusive lock [not for Cortex-M0 variants]. More...
uint32_t | __SSAT (unint32_t value, uint32_t sat)
| Signed Saturate [not for Cortex-M0 variants]. More...
uint32_t | __USAT (uint32_t value, uint32_t sat)
| Unsigned Saturate [not for Cortex-M0 variants]. More...
uint8_t | __CLZ (uint32_t value)
| Count leading zeros [not for Cortex-M0 variants]. More...

## Description

The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler.

## Function Documentation

void __BKPT | ( | uint8_t | value | ) |

This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

Parameters

  [in] | value | is ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint.

void __CLREX | ( | void |  | ) |

This function removes the exclusive lock which is created by LDREX [not for Cortex-M0 variants].

uint8_t __CLZ | ( | uint32_t | value | ) |

This function counts the number of leading zeros of a data value [not for Cortex-M0 variants].

Parameters

  [in] | value | Value to count the leading zeros

Returns
  number of leading zeros in value

void __DMB | ( | void |  | ) |

This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

void __DSB | ( | void |  | ) |

This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

void __ISB | ( | void |  | ) |

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

uint8_t __LDREXB | ( | volatile uint8_t * | addr | ) |

This function performs a exclusive LDR command for 8 bit value [not for Cortex-M0 variants].

Parameters

  [in] | *addr | Pointer to data

Returns
  value of type uint8_t at (*addr)

uint16_t __LDREXH | ( | volatile uint16_t * | addr | ) |

This function performs a exclusive LDR command for 16 bit values [not for Cortex-M0 variants].

Parameters

  [in] | *addr | Pointer to data

Returns
  value of type uint16_t at (*addr)

uint32_t __LDREXW | ( | volatile uint32_t * | addr | ) |

This function performs a exclusive LDR command for 32 bit values [not for Cortex-M0 variants].

Parameters

  [in] | *addr | Pointer to data

Returns
  value of type uint32_t at (*addr)

void __NOP | ( | void |  | ) |

This function does nothing. This instruction can be used for code alignment purposes.

uint32_t __RBIT | ( | uint32_t | value | ) |

This function reverses the bit order of the given value [not for Cortex-M0 variants].

Parameters

  [in] | value | Value to reverse

Returns
  Reversed value

uint32_t __REV | ( | uint32_t | value | ) |

This function reverses the byte order in integer value.

Parameters

  [in] | value | Value to reverse

Returns
  Reversed value

uint32_t __REV16 | ( | uint32_t | value | ) |

    This function reverses the byte order in two unsigned short values.

Parameters

  [in] | value | Value to reverse

Returns
  Reversed value

Note
  The function can be disabled by defining the compile time flag __NO_EMBEDDED_ASM. This rule applies to the ARM toolchain. For example:
  #ifndef __NO_EMBEDDED_ASM
  __REV16(0x1);
  #endif

int32_t __REVSH | ( | int32_t | value | ) |

    This function reverses the byte order in a signed short value with sign extension to integer.

Parameters

  [in] | value | Value to reverse

Returns
  Reversed value

Note
  The function can be disabled by defining the compile time flag __NO_EMBEDDED_ASM. This rule applies to the ARM toolchain. For example:
  #ifndef __NO_EMBEDDED_ASM
  __REVSH(0x1);
  #endif

uint32_t __ROR | ( | uint32_t | value,
|  | uint32_t | shift
| ) |  |

This function rotates a value right by a specified number of bits.

Parameters

  [in] | value | Value to be shifted right
  [in] | shift | Number of bits in the range [1..31]

Returns
  Rotated value

void __SEV | ( | void |  | ) |

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

uint32_t __SSAT | ( | unint32_t | value,
|  | uint32_t | sat
| ) |  |

This function saturates a signed value [not for Cortex-M0 variants].

Parameters

  [in] | value | Value to be saturated
  [in] | sat | Bit position to saturate to [1..32]

Returns
  Saturated value

uint32_t __STREXB | ( | uint8_t | value,
|  | volatile uint8_t * | addr
| ) |  |

This function performs a exclusive STR command for 8 bit values [not for Cortex-M0 variants].

Parameters

  [in] | value | Value to store
  [in] | *addr | Pointer to location

Returns
  0 Function succeeded
  1 Function failed

uint32_t __STREXH | ( | uint16_t | value,
|  | volatile uint16_t * | addr
| ) |  |

This function performs a exclusive STR command for 16 bit values [not for Cortex-M0 variants].

Parameters

  [in] | value | Value to store
  [in] | *addr | Pointer to location

Returns
  0 Function succeeded
  1 Function failed

uint32_t __STREXW | ( | uint32_t | value,
|  | volatile uint32_t * | addr
| ) |  |

This function performs a exclusive STR command for 32 bit values [not for Cortex-M0 variants].

Parameters

  [in] | value | Value to store
  [in] | *addr | Pointer to location

Returns
  0 Function succeeded
  1 Function failed

uint32_t __USAT | ( | uint32_t | value,
|  | uint32_t | sat
| ) |  |

This function saturates an unsigned value [not for Cortex-M0 variants].

Parameters

  [in] | value | Value to be saturated
  [in] | sat | Bit position to saturate to [0..31]

Returns
  Saturated value

void __WFE | ( | void |  | ) |

Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs:

- If the event register is 0, then WFE suspends execution until one of the following events occurs:
  - An exception, unless masked by the exception mask registers or the current priority level.
  - An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
  - A Debug Entry request, if Debug is enabled.
  - An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.

- If the event register is 1, then WFE clears it to 0 and returns immediately.

void __WFI | ( | void |  | ) |

WFI is a hint instruction that suspends execution until one of the following events occurs:

- A non-masked interrupt occurs and is taken.
- An interrupt masked by PRIMASK becomes pending.
- A Debug Entry request.